Intern - Layout Analog Design

About the role

Renesas is looking for a motivated Bachelor student in Electronic Engineering to complete a six-month internship at its new design centre in Catania, Italy. The intern joins the Performance Computing Power team and works alongside experienced engineers who give guidance and support. The objective is research and development in analog and mixed-signal circuit layout, with a focus on Power Management ICs and Smart Power Stages for high-performance computing.

Key responsibilities

• Conceive the layout of analog and mixed-signal circuit blocks.
• Study every step of layout conception, from floor plan through routing, checks and extraction.
• Learn and apply different layout techniques, including matching constraints, electromigration studies and layout side effects.
• Familiarise yourself with layout tools such as Cadence, Calibre and VXL.
• Ensure layout quality and compliance with specifications.

Required profile

• Bachelor student in Electronic Engineering.
• Basic knowledge of CMOS and bipolar transistors, diodes, resistors, capacitors and inductors.
• Knowledge of voltage and current references, current mirrors, amplifiers, comparators, oscillators and clocking circuits, and digital gates.
• Good communication skills and good knowledge of written and spoken English.

Required skills

• Familiarity with the Cadence design environment is a plus.