Senior Analog IC Layout Engineer - MCU

About the role

The Senior Analog IC Layout Engineer will lead the physical implementation of complex analog, mixed‑signal and custom digital blocks, driving projects from floor‑planning through tape‑out while ensuring performance, reliability and schedule targets are met.

Key responsibilities

• Lead layout implementation of analog, mixed‑signal and custom digital blocks, including floor‑planning, device matching, routing and optimization.
• Perform and review physical verification (DRC, LVS, ERC, EM/IR, latch‑up, density, reliability) and collaborate with design, verification, technology and product teams to resolve layout challenges.
• Support advanced‑node technologies such as FinFET processes and contribute to methodology improvements.
• Provide technical guidance and mentorship to junior engineers and contractors.
• Assess project risks, estimate layout effort and drive execution to meet aggressive schedules.

Required profile

• BSEE or MSEE with 8‑12+ years of custom analog/mixed‑signal layout experience in deep sub‑micron CMOS.
• Proven track record of successful tape‑outs and delivery of high‑quality silicon.
• Strong communication and cross‑functional leadership skills.

Required skills

• Expertise in analog layout techniques: matching, common centroid, shielding, noise isolation, ESD‑aware layout, power distribution, high‑performance routing.
• Proficiency with Cadence Virtuoso XL, floor‑planning, constraint‑driven layout and PVS DRC/LVS/ERC tools.
• Knowledge of semiconductor process technologies including planar and FinFET nodes.
• Experience with matching, EM/IR analysis, high‑speed routing, parasitics and DFM practices.
• Familiarity with PLL, OSC, ADC, DAC, LDO, bandgap and high‑speed interface circuits.
• SKILL or Perl scripting (optional).