Junior Physical Design Engineer - MCU

About the role

NXP is expanding its Catania team to develop high‑impact micro‑controllers for AI at the Edge. As a Junior Physical Design Engineer you will support the RTL‑to‑GDSII implementation flow for complex SoC/MCU designs on advanced nodes.

Key responsibilities

• Support SOC‑level floorplanning, power grid design, IO placement, place & route, clock‑tree synthesis and physical verification (DRC, LVS, ERC, Antenna).
• Assist with tool setup, static timing analysis, timing constraints, IR‑drop and electromigration analysis.
• Collaborate with RTL, DFT and analog teams for smooth design hand‑offs.
• Maintain and extend automation scripts (TCL, Python, Perl) to improve flow efficiency.
• Learn and apply state‑of‑the‑art EDA tools and work with vendors to troubleshoot issues.

Required profile

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering or related field.
• Solid understanding of digital design principles, semiconductor physics and IC fundamentals.
• Familiarity with basic IC design flow from RTL to GDSII and basic timing analysis.
• Basic knowledge of scripting languages such as TCL, Python or Perl.
• Excellent English communication skills and strong analytical mindset.

Required skills

• Floorplanning, power grid design, IO placement, place & route, clock‑tree synthesis.
• Physical verification tools (DRC, LVS, ERC, Antenna).
• Static timing analysis and timing constraints management.
• IR‑drop and electromigration analysis (e.g., Ansys RedHawk, Cadence Voltus).
• Scripting in TCL, Python, Perl.
• Experience with Synopsys Fusion Compiler, ICC2, Formality or Cadence Innovus, Genus.
• Basic knowledge of UPF/CPF low‑power techniques.