Analog Layout Intern

About the role

Marvell is recruiting an Analog Layout Intern for its Pavia office, within a small analog team of Central Engineering. The internship lasts up to 6 months and gives exposure to IC design engineering skills and tools. The successful candidate is self-motivated, eager to learn new technologies and able to work effectively in a talented group.

Key responsibilities

• Learn the use of IC layout development CAD and physical verification tools.
• Train on mask/layout design using Cadence Virtuoso EXL and Custom Compiler Synopsys, with circuit design as input.
• Learn design rules of advanced CMOS technology nodes (16nm to 3nm).
• Run DRC/LVS checks.
• Learn electromigration/IR drop (EMIR) concepts for analog IC layout.
• Optimize layout designs in terms of area and parasitic R, C.
• Collaborate with the team, attend routine meetings with a technical mentor and the layout and project teams, and present issues or solutions encountered.

Required profile

• Student of electronics or a similar technical field enrolled at an accredited Italian university, or a Bachelor/Master graduate.
• Fundamental understanding of basic electronic concepts, typically from an Electronics Engineering degree or similar.
• Some specialized coursework in analog design or layout, as part of a degree, summer or conference courses, is a valuable asset.
• Understanding of circuit elements (diode, transistor, capacitor, resistor) and basic digital fundamentals (latches, flip-flops, combinatorial logic).
• Excellent communication skills, fluency in English and enough Italian, and eligibility to work in Italy without restrictions.

What we offer

• Expected base pay of 21,250 to 28,750 EUR per year, depending on skills, experience, qualifications, location and market conditions.
• Competitive compensation and benefits.