Analog Layout Manager

About the role

Marvell is seeking an experienced Analog Layout Manager to lead a small but impactful analog team within its Central Engineering group. The role combines strategic leadership with hands‑on macro‑level layout work on cutting‑edge semiconductor technologies.

Key responsibilities

• Lead and mentor a team of full‑time and contract analog layout designers.
• Plan, execute and track layout schedules for analog macros, assessing risks and floor‑plan constraints.
• Perform hands‑on layout work on macro‑level designs using Cadence or Synopsys tools.
• Collaborate with global engineering teams across the Americas, APAC and Europe on project deliverables.
• Hire additional designers as needed and manage resource allocation.

Required profile

• 10+ years of analog layout design experience.
• 3+ years of management or team‑lead experience.
• Strong analytical and problem‑solving abilities.
• Excellent verbal and written communication, with experience in conflict resolution.

Required skills

• Deep knowledge of layout methodology from chip planning to tape‑out.
• Experience with advanced process technologies, preferably FinFET.
• Proficiency in LVS, DRC debugging and interpreting Calibre DRC, ERC, LVS reports.
• Expert use of Cadence or Synopsys layout entry tools.
• Programming/scripting skills in Skill, TCL or Perl (optional but beneficial).