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Principal Digital Design Engineer

analogdevices · Bari

New
Senior 52,360 - 75,820 EUR/year 🇬🇧 English
RTL FPGA SoC UVM Synthesis Timing analysis ATPG

Job description

About the role

Analog Devices is looking for a Principal Digital Design Engineer to join its Digital Healthcare IC design team in Bari, Italy. The team develops integrated circuits for disease management, patient monitoring and smart hospital applications, combining signal processing with sensors and packaging innovations. The engineer works with a global team and leads the digital part of new mixed-signal products, from early architecture through design-in and characterization.

Key responsibilities

  • Drive projects across milestones to tape-out of Application Specific Standard Products (ASSP), from architecture discussions through design-in (IC and/or FPGA) and characterization support.
  • Act as digital lead on key projects and help define top-level chip requirements.
  • Use recommended design and verification techniques, tools and flows to produce efficient designs meeting functional, power and timing objectives.
  • Work with Product, Test, Marketing and Application engineers, importing and exporting information as needed.
  • Mentor junior design engineers and document, present and take part in project meetings.
  • Project and personnel leadership responsibilities may be assigned to highly qualified candidates.

Required profile

  • Electrical Engineering degree with 7+ years of relevant experience in mixed-signal digital design.
  • Track record of successful product development from RTL to GDSII.
  • Experience with full-chip verification, regressions and mixed-signal designs.
  • Strong analytical, problem-solving, teamwork and communication skills.
  • Preferred: scripting languages (Python, Perl or Shell), mixed-signal verification methodology, UVM, and verification of ARM or RISC-V subsystems or SoCs.

Required skills

  • Digital design with RTL, SystemVerilog, standard cells and FPGA designs.
  • Complex SoC architecture design and ASSP architecture definition.
  • Chip and block-level verification, synthesis, timing analysis and scan/ATPG.
  • Silicon debug and testbench FPGA support.

What we offer

  • The pay range for the position in Milan is EUR 52,360 to EUR 75,820, which may vary by location and level.
  • Discretionary performance-based bonus, possible variable compensation, paid annual leave and supplemental benefits depending on local policy.
  • A collaborative, growth-focused environment with work-life balance.

Questions fréquentes

Le salaire proposé pour ce poste est de 52-76k EUR par an. Le détail figure dans l'annonce.
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Published 16 hours ago

Expires 1 month from now

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analogdevices

Bari