Principal Layout Engineer

About the role

NXP's Smart Analog Interfaces team is looking for a Principal Analog Layout Engineer to lead and execute analog and mixed‑signal layout projects for consumer and automotive applications.

Key responsibilities

• Develop and lead block‑level and top‑level analog/mixed‑signal layouts, including floorplanning, power routing, ESD implementation and chip integration.
• Run and debug DRC, LVS, ERC and extraction flows, and provide layout schedules and technical leadership.
• Collaborate with circuit designers, digital P&R, IO, package, test and PDK teams to resolve design risks and PDK issues.
• Improve layout methodologies, automation and documentation.

Required profile

• BSEE or MSEE with at least 10 years of custom analog/mixed‑signal layout experience in deep sub‑micron CMOS.
• Proven experience leading analog‑on‑top and digital‑on‑top chip layouts.
• Excellent communication and cross‑functional leadership skills; fluent in English.

Required skills

• Cadence Virtuoso XL, floorplanning, constraint‑driven layout, PVS DRC/LVS/ERC.
• Strong knowledge of matching, common centroid, shielding, EM/IR, high‑speed routing, parasitics and DFM practices.
• Experience with PLL, OSC, ADC, DAC, LDO, bandgap and high‑speed interface circuits.
• SKILL or Perl scripting (plus).

What we offer

• Gross annual base salary between 61,000 € and 83,900 €.
• Potential annual incentive, equity and competitive benefits package.