Principal Physical Design Engineer - MCU

About the role

NXP is expanding its Catania team to develop high‑impact micro‑controllers for AI at the Edge. The Principal Physical Design Engineer will lead the physical implementation of complex, high‑performance semiconductor ICs.

Key responsibilities

• Floorplanning, power grid design, place and route, low‑power implementation, clock tree synthesis, and timing closure.
• Perform static timing analysis, power and signal integrity analysis, and physical verification (DRC/LVS/Antenna).
• Collaborate with architecture, RTL, DFT, and package teams to ensure seamless integration.
• Mentor junior and senior physical design engineers and drive adoption of new EDA tools.

Required profile

• Bachelor’s degree with 12+ years or Master’s with 10+ years of relevant experience.
• Experience with advanced technology nodes 16 ff and below.
• Strong problem‑solving, analytical, and communication skills.

Required skills

• Cadence Innovus, Synopsys Fusion Compiler/ICC2, Ansys RedHawk/PowerSI.
• Synopsys PrimeTime, UPF/CPF, clock gating, power intent.
• Physical verification tools: Synopsys IC Validator, Cadence Pegasus/PVS, Mentor Calibre.
• Scripting in Tcl, Python, Perl.

What we offer

• Gross annual base salary between 61,000 € and 83,900 €.
• Potential annual incentive, equity, and competitive benefits.